Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for processing instructions in an instruction pipeline.
Description of the Related Art
Modern day processor systems tend to be structured in multiple stages in a pipelined fashion. Typical pipelines often include separate units for fetching instructions, decoding instructions, mapping instructions, executing instructions, and then writing results to another unit, such as a register. An instruction fetch unit of a microprocessor is responsible for providing a constant stream of instructions to the next stage of the processor pipeline. Typically, fetch units utilize an instruction cache in order to keep the rest of the pipeline continuously supplied with instructions. The sequence of instructions being fetched is based upon a prediction of the program flow, which is normally sequential. However, branch instructions can change the sequential nature of program flow. Therefore, accurate prediction of branch instructions can ensure the fetch unit continues to fetch instructions down the correct path.
For some implementations of processor pipelines, the program instructions may include if-then (IT) instructions. An IT instruction is used to predicate a predetermined number of the following instructions. The IT instruction along with the instructions that follow the IT instruction and that are controlled by the IT instruction may be referred to herein as an “IT instruction block”. The IT instruction specifies a condition and indicates for each of the following instructions in the IT instruction block whether the true or false result for the condition causes the instruction to be executed. If one of the instructions in the block is an unconditional branch, then the IT instruction effectively changes the unconditional branch into a conditional branch. However, in some processor pipelines, it may be difficult to determine early in the pipeline if an unconditional branch that follows closely behind an IT instruction is actually part of the IT instruction block. If the branch prediction mechanism of the processor waits to predict the branch direction of an unconditional branch until after the IT instruction block boundaries are resolved, this may result in a large performance penalty by staying too long on the wrong fetch path.